In read operations for conventional semiconductor memory devices, such as synchronous dynamic random access memory (SDRAM) devices or asynchronous dynamic random access memory (DRAM) devices, a row address is specified for use with a column address. Column address changes are detected by a circuit that provides a timing pulse that enables the data output register after a fixed predetermined delay. The length of the delay must provide for precharging, address decoding, sensing and driving for the longest read operation so that the data that is latched in the data output register represents the data that has been read from the memory array and not spurious signals.
The data output path includes sense amplifier circuits which are located at the output of the memory array for amplifying data read out of the memory array. Data amplified by the sense amplifiers is transferred through data read lines to the data output register which latches the data read from the memory array. The data output register is located physically adjacent to data input/output pins of the chip on which the memory array is fabricated. The physical separation between the sense amplifiers and the data output data register introduces a propagation delay between the time that valid data is available at the output of the memory array and the time that the data is latched in the data output register. The read out of new data must be delayed until the data read out of the memory array has been latched in the data output register. Sufficient time must be provided to allow the data signals to propagate down to the end of the chip before the data output register is clocked to latch the data signals into the data output register.
The delay provided may be too short for some memory cells and sense amplifiers that respond relatively slowly due to their physical location on the chip. In such a case, the data output register could be enabled at a time which spurious signals exist on the data output path. If the delay is long enough to avoid all spurious signals, data from faster cells accessed will wait at the data output register before the data output register is clocked. A faster access time would have been possible had the delay been shorter.
A further consideration is that in known memory systems, the data read lines are precharged between every data read cycle. Time must be provided to complete the precharging before applying the data read from the memory array to the data read lines for transfer to the data output register. This further limits the ability to provide faster cycle times for the memory system.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to minimize the time required for transferring data read out of a semiconductor memory system to the data output register of the memory system to allow faster cycle times for the memory system.